Computing hardware and software



An important goal of the USQCD collaboration has been the construction, efficient programming, and dedicated use of a multi-teraflop/s QCDOC computer. The QCDOC (Quantum Chromodynamics on a Chip) project has culminated in the construction of three 12,288-processor 10 teraflop/s (peak) computers optimized for lattice QCD calculations.

The QCDOC machines are constructed of small, low-power processing nodes made up of a single IBM-manufactured ASIC (Applications Specific Integrated Circuit) with a companion 128-Mbyte memory module (below). These nodes are interconnected with a 6-dimensional toroidal mesh network. The design was begun in 1999, prototype hardware was available for testing as part of the SciDAC effort in the fall of 2003, and the three large machines were completed in the Spring of 2005.

A two-node QCDOC daughter card.

The SciDAC-developed high-performance, level-3 inverters for the Dirac operator were used extensively in testing the QCDOC design and in establishing the validity of the resulting hardware. The QCD API permitted the porting of the MILC and Chroma codes to QCDOC, making this specialized machine efficiently available to the broader U.S. lattice QCD community. This extensive software preparation and the resulting demonstration of efficient operation provided an essential foundation for the U.S. proposal to the HEP and NP Programs of the DOE for the funding of the U.S. QCDOC machine. The top figure shows the installation of this computer together with a companion RIKEN-funded one. Both are now in full operation at the Brookhaven National Laboratory. The DOE-funded machine is carrying out a physics program organized by the Scientific Program Committee of the USQCD Collaboration.